The present invention relates generally to semiconductor device fabrication and more particularly to wet clean stripping of dry etch residue in trench-first dual damascene process for fabricating semiconductor devices.
In a self-aligned dual damascene or trench-first dual damascene formation process, two hard mask layers provided over the inter-metal dielectric (IMD) layer are used to form the trench and via opening patterns. The trench openings are patterned over the first or the top-most hard mask layer. This is followed by patterning and etching via openings over the second hard mask layer within the patterned trench openings. Next, the trench and via patterns are simultaneously etched into the IMD layer using both hard mask layers etching masks.
The etching of the IMD layer is accomplished by dry plasma etching. During the plasma etching of the IMD layer, the hard mask layer materials often interact with the photoresist and leaves residual polymeric etching contaminants along the sidewalls and bottom of the dual damascene trench via pattern openings. In trench-first dual damascene processes utilizing TiN metal hard mask as one of the two hard mask layers, the dry plasma etching process tend to produce two types of polymer residue contaminants, carbon-rich polymer and Ti-rich polymer contaminants. These polymeric contaminants can interfere with the subsequent metal filling of the dual damascene openings and degrade electrical performance and reliability of the dual damascene structure. In conventional trench-first dual damascene processes, two separate wet clean process steps, one strong alkaline based and one strong acid based are used in an attempt to clean the residues. But having two separate wet clean processes are costly and also has the unwanted side-effect of attacking too much of the copper metal in the metal layer below.